TY - GEN
T1 - An architectural level design methodology for embedded face detection
AU - Kianzad, V.
AU - Saha, S.
AU - Schlessman, J.
AU - Aggarwal, G.
AU - Bhattacharyya, S. S.
AU - Wolf, W.
AU - Chellappa, R.
PY - 2005
Y1 - 2005
N2 - Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features.
AB - Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, including banking and security system access control, video surveillance, and multimedia information retrieval. In this paper, we discuss an architectural level design methodology for implementation of an embedded face detection system on a reconfigurable system on chip. We present models for performance estimation and validate these models with experimental values obtained from implementing our system on an FPGA platform. This modeling approach is shown to be efficient, accurate, and intuitive for designers to work with. Using this approach, we present several design options that trade-off various architectural features.
KW - Design space exploration
KW - Face detection
KW - Reconfigurable plat-forms
KW - System-level models
UR - http://www.scopus.com/inward/record.url?scp=27644592388&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=27644592388&partnerID=8YFLogxK
U2 - 10.1145/1084834.1084872
DO - 10.1145/1084834.1084872
M3 - Conference contribution
AN - SCOPUS:27644592388
SN - 1595931619
SN - 9781595931610
T3 - CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis
SP - 136
EP - 141
BT - CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and Systems Synthesis
PB - Association for Computing Machinery
T2 - 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis CODES+ISSS 2005
Y2 - 18 September 2005 through 21 September 2005
ER -