This paper presents a hardware architecture for embedded real-time model predictive control (MPC). The computational cost of an MPC problem, which relies on the solution of an optimization problem at every time step, is dominated by operations on real matrices. In order to design an efficient and low-cost application-specific processor, we analyze the computational cost of MPC, and we propose a limited-resource host processor to be connected with an application-specific matrix coprocessor. The coprocessor uses a 16-b logarithmic number system arithmetic unit, which is designed using cotransformation, to carry out the required arithmetic operations. The proposed architecture is implemented by means of a hardware description language and then prototyped and emulated on a field-programmable gate array. Results on computation time and architecture area are presented and analyzed, and the functionality of the proposed architecture is verified using two case studies: a linear problem of a rotating antenna and a nonlinear glucose-regulation problem. The proposed MPC architecture yields a small-in-size and energy-efficient implementation that is capable of solving the aforementioned problems on the order of milliseconds, and we compare its performance and area requirements with other MPC designs that have appeared in the literature.
- Embedded systems
- Logarithmic number system (LNS)
- Model predictive control (MPC)
- Optimal control
ASJC Scopus subject areas
- Control and Systems Engineering
- Electrical and Electronic Engineering