A custom-made algorithm-specific processor for model predictive control

Panagiotis D. Vouzis; Leonidas G. Bleris; Mark G. Arnold; Mayuresh V. Kothare

doi:10.1109/ISIE.2006.295597

A custom-made algorithm-specific processor for model predictive control

Panagiotis D. Vouzis, Leonidas G. Bleris, Mark G. Arnold, Mayuresh V. Kothare

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

This paper presents an algorithm-specific processor for embedded Model Predictive Control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit Logarithmic Number System (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a Hardware Description Language (HDL) and subsequently it is synthesized and emulated on a Field Programmable Gate Array (FPGA). The timing and area cost results are presented and analyzed.

Original language	English (US)
Title of host publication	IEEE International Symposium on Industrial Electronics
Pages	228-233
Number of pages	6
Volume	1
DOIs	https://doi.org/10.1109/ISIE.2006.295597
State	Published - 2006
Externally published	Yes
Event	International Symposium on Industrial Electronics 2006, ISIE 2006 - Montreal, QC, Canada Duration: Jul 9 2006 → Jul 13 2006

Other

Other	International Symposium on Industrial Electronics 2006, ISIE 2006
Country/Territory	Canada
City	Montreal, QC
Period	7/9/06 → 7/13/06

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Systems Engineering

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10.1109/ISIE.2006.295597

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@inproceedings{abeb0cfb51db40e58bcc6631ba772da6,

title = "A custom-made algorithm-specific processor for model predictive control",

abstract = "This paper presents an algorithm-specific processor for embedded Model Predictive Control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit Logarithmic Number System (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a Hardware Description Language (HDL) and subsequently it is synthesized and emulated on a Field Programmable Gate Array (FPGA). The timing and area cost results are presented and analyzed.",

author = "Vouzis, {Panagiotis D.} and Bleris, {Leonidas G.} and Arnold, {Mark G.} and Kothare, {Mayuresh V.}",

year = "2006",

doi = "10.1109/ISIE.2006.295597",

language = "English (US)",

isbn = "1424404975",

volume = "1",

pages = "228--233",

booktitle = "IEEE International Symposium on Industrial Electronics",

note = "International Symposium on Industrial Electronics 2006, ISIE 2006 ; Conference date: 09-07-2006 Through 13-07-2006",

}

TY - GEN

T1 - A custom-made algorithm-specific processor for model predictive control

AU - Vouzis, Panagiotis D.

AU - Bleris, Leonidas G.

AU - Arnold, Mark G.

AU - Kothare, Mayuresh V.

PY - 2006

Y1 - 2006

N2 - This paper presents an algorithm-specific processor for embedded Model Predictive Control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit Logarithmic Number System (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a Hardware Description Language (HDL) and subsequently it is synthesized and emulated on a Field Programmable Gate Array (FPGA). The timing and area cost results are presented and analyzed.

AB - This paper presents an algorithm-specific processor for embedded Model Predictive Control (MPC). After analyzing the computational cost of MPC, via profiling, we observe that the optimizations associated with MPC are dominated by operations on real matrices. To overcome this bottleneck we propose connecting a limited resource host processor with an algorithm-specific matrix processor, whose architecture is described. The matrix processor uses a 16-bit Logarithmic Number System (LNS) arithmetic unit to carry out the required arithmetic operations. The proposed architecture is implemented using a Hardware Description Language (HDL) and subsequently it is synthesized and emulated on a Field Programmable Gate Array (FPGA). The timing and area cost results are presented and analyzed.

UR - http://www.scopus.com/inward/record.url?scp=34547968459&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547968459&partnerID=8YFLogxK

U2 - 10.1109/ISIE.2006.295597

DO - 10.1109/ISIE.2006.295597

M3 - Conference contribution

AN - SCOPUS:34547968459

SN - 1424404975

SN - 9781424404971

VL - 1

SP - 228

EP - 233

BT - IEEE International Symposium on Industrial Electronics

T2 - International Symposium on Industrial Electronics 2006, ISIE 2006

Y2 - 9 July 2006 through 13 July 2006

ER -

A custom-made algorithm-specific processor for model predictive control

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