A 2-MHZ, process and voltage compensated clock oscillator for biomedical implantable SoC in 0.18-μm CMOS

Hansraj Bhamra, Pedro Irazoqui

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present the design and performance of a power and area efficient, process and voltage compensated, 2-MHz clock oscillator for state-of-the art wireless biomedical implantable systems-on-chip. The design presented in this paper is based on a fully differential three-stage ring oscillator with replica feedback bias, a novel process detection circuit, and a novel differential comparator to save power and area. The design of the comparator ensures the rail-to-rail swing and further improves power-supply-rejection-ratio (PSRR). The process corner sensing scheme is based on the leakage current of the device which generates control voltage for the replica feedback bias circuit. A total of 66 chip samples were collected from various locations on multiple full wafers and average variation of ±2.81% with process corner was measured at room temperature. The variation in clock frequency with supply was 0.11% for the voltage range of 1.9V-3V. The design of oscillator is intended for the RF powering scheme and it occupies 0.018 μm2 in 0.18-μm CMOS. The clock oscillator consumes 12μW from a 1.8 V regulated supply.

Original languageEnglish (US)
Title of host publication2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Pages618-621
Number of pages4
DOIs
StatePublished - 2013
Externally publishedYes
Event2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013 - Beijing, China
Duration: May 19 2013May 23 2013

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Country/TerritoryChina
CityBeijing
Period5/19/135/23/13

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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